车用悬挂式时钟速度显示电路设计

本研究完成了车用计时计速器的设计工作。对单元电路进行了SPICE-Ⅱ电路模拟,对逻辑设计在DA1SY工作站上进行了逻辑模拟,以检查设计工作的正确性。版图设计采用5μm铝栅自对准CMOS设计规则并在SX-8000系统上完成了版图输入及检查工作。本研究系国产第一片汽车专用计时计速电路的研究,电路投产成功后,将会产生相当的社会效益与经济效益,并为开发新一代汽车专用IC及推进其国产化进程打下基础。

Circuits Design of Hanging Clock and Speed Display for Automobiles

In this paper, The designing of the clock speedometer IC is introduced. The cell circuit design and logic design are examined and proved by circuit simulation with SPICE-2 and logic simulation in function. level in Daisy work station. The regulation of the layout design is adopted with 5 um al-gate self-alignment. CMOS design rules. The layout is finished in SX-8000 MDS system. Interactive design rule checking is done for every layout cell to prove the layout, whether correct or incorrect. In this paper, The first AASIC's clock speedometer has been developed. It will be benificial to the society and economy, and lay the foundation of developing a new generation AASIC. And also it will carry the localization a step forward.