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An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols
Authors:Fredrik Dahlgren  Jonas Skeppstedt  Per Stenström
Affiliation:

Department of Computer Engineering, Chalmers University of Technology, SE-412 96, Gothenburg, Sweden

Abstract:Coherence misses and invalidation traffic limit the performance of bus-based multiprocessors using write-invalidate snooping caches. This paper considers optimizations of a write-invalidate protocol that remove such overhead. While coherence misses are attacked by a hybrid update/invalidate protocol and another technique where update instructions are selectively inserted by a compiler, invalidation traffic is reduced by three optimizations that coalesce ownership acquisition with miss handling: migrate-on-dirty, an adaptive hardware-based scheme, and compiler-controlled insertion of load-exclusive instructions.

The relative effectiveness of these optimizations are evaluated using detailed architectural simulations and a set of four parallel programs. We find that while both of the update-based schemes effectively remove most coherence misses, the hybrid update/invalidate scheme causes lower traffic. By contrast, the compiler-based approach to cut invalidation traffic is slightly more efficient than the adaptive hardware-based scheme. Moreover, the migrate-on-dirty heuristic is found to have devastating effects on the miss rate.

Keywords:Shared-memory multiprocessors  Snoopy cache protocols  Dataflow analysis techniques  Performance evaluation
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