基于FPGA的控制系统高速总线的设计与实现

为了提高控制系统的通信速度和效率,研究高速总线的系统架构,设计并实现具有高实时性,高吞吐率,易扩展等特点的基于现场可编程逻辑门阵列(FPGA)的控制系统高速总线(LHSB),物理层采用多点低压差分信号(M-LVDS)标准,实现256 Mbps的高速串行通信,数据链路层通过实时的链路状态维护实现多路径优化选择的网络冗余,保证通信可靠性的同时使带宽的利用率最大化.通过Xilinx XC3S400A FPGA对设计方案进行实现和实际测试,结果表明,高速总线与当前主流的控制系统总线相比,通信速度和实时性能有了明显的提升,并最大程度的满足上层应用的需要.

Design and implementation of FPGA based high-speed bus for control system

The system architecture of high-speed bus was studied to improve the control system communication speed and efficiency. A FPGA based high-speed bus applied in control system was designed and implemented, which is high real time, high throughput, easy to expand and so on. The physical layer was based on multipoint-low-voltage differential signaling (M LVDS) standard to achieve 256 Mbps serial communication. Multi-path optimization selection network redundancy through real-time link state maintenance was used in data link layer to ensure reliable communications while maximizing bandwidth utilization. The design was implemented on Xilinx XC3S400A FPGA and actual tests were done. Results show that communication speed and real-time performance are improved significantly compared with the current mainstream bus of control system, and the needs of upper applications are met to the greatest degree．