|
|||||
|
|
Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs |
|
| Authors: | Kishine K. Inaba H. Nakamura Ma. Nakamura Mi. Ohtomo Y. Onodera H. |
| Affiliation: | University of Shiga Prefecture; |
| Abstract: | A low-jitter design method based on vn-domain jitter analysis for the clock and data recovery (CDR) ICs using the linear phase-locked loop (PLL) is proposed. Using this method, the loop parameters of the PLL can be optimised, which makes it possible to design the CDR IC for various targets. |
| Keywords: | |