| 一种新的8B/10B编解码硬件设计方法 |
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| 引用本文： | 贺传峰,戴居丰,毛陆虹. 一种新的8B/10B编解码硬件设计方法[J]. 高技术通讯, 2005, 15(3): 48-52 |
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| 作者姓名： | 贺传峰 戴居丰 毛陆虹 |
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| 作者单位： | 天津大学电子信息工程学院光纤通信研究所,天津,300072;天津大学电子信息工程学院光纤通信研究所,天津,300072;天津大学电子信息工程学院光纤通信研究所,天津,300072 |
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| 基金项目： | 863计划 (2 0 0 2AA3 12 2 40 ,2 0 0 3AA3 12 0 40 )资助项目 |
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| 摘 要： | 在深入研究了8B／10B编码规则及其内在相关性的基础上，提出了一种新的8B／10B编、解码方法，该方法综合了查表法和逻辑运算法的优点，具有运算量小、编解码同步好、速度快、可靠性高等优点。用Verilog HDL语言实现编解码算法的描述，并通过高性能的FPGA器件进行仿真和综合，实现了具体的硬件电路，并验证了设计方法的有效性和可行性。
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| 关 键 词： | 8B/10B码 编码 解码 光纤通信 集成电路 |
A new hardware implementing design of 8B/10B encoding and decoding |
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| He Chuanfeng,Dai Jufeng,Mao Luhong. A new hardware implementing design of 8B/10B encoding and decoding[J]. High Technology Letters, 2005, 15(3): 48-52 |
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| Authors: | He Chuanfeng Dai Jufeng Mao Luhong |
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| Abstract: | The encoding rule of 8B/10B and inherent relationship among 8B/10B codes were deeply investigated in this paper. A new implementing method of 8B/10B encoding and decoding is introduced. It combines the advantages of lookup-table and logic analysis methods with low computation complexity, easy synchronization, high speed and high reliability. The arithmetic of encoding and decoding is described with Verilog HDL, and was simulated and synthesized with high performance FPGA. So the hardware circuit is realized to validate the feasibility of this method. |
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| Keywords: | 8B/10B code encoding decoding fiber communication integrated circuit |
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