Negative Save Sign Extension for Multi-term Adders and Multipliers |
| |
| Authors: | Robert T. Grisamore,Earl E. Swartzlander Suffix" >Jr. |
| |
| Affiliation: | (1) Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX 78712, USA |
| |
| Abstract: | This paper outlines a new sign extension technique for use in carry save adder trees that reduces the computational complexity. The “Negative Save” technique presented is a modification to the Baugh–Wooley sign extension technique developed for array multipliers. Applying this sign extension technique to both parallel adder and multiplier partial product structures reduces the hardware required. The speed of the resulting structures is also improved. |
| |
| Keywords: | adder trees multi-term adders multipliers two’ s complement arithmetic sign extension |
| 本文献已被 SpringerLink 等数据库收录！ |
