Matlab／Simulink到VHDL代码的转换研究及其实验配置

讨论了由Mattab／Simutink生成VHDL代码的原理。详细论述了从Simulink模型顶层系统设计、IP核配置到到VHDL语言自动转换、综合、适配与时序仿真的结构与流程。介绍了利用Xilinx的System Generator及Altera的DSP Builder将Simulink模型转换为VHDL代码的方法，对算法实现过程中需注意的问题进行了说明。提出了基于最新版本的完整实验室软硬件配置方案。利用Xilinx Blockset的Mcode模块设计一个带延迟的复数乘法器并进行了软硬件的仿真测试。

Study of VHDL Conversion from Matlab/ Simulink and Experiment Device

The principles of VHDL code generated by Matlab/Simulink is discussed in this paper, detail of the structure and processes from Simulink models top system design, IP configuration to the nuclear VHDL automatic conversion,integrated,time series simulation and adaptation are given. The elements and flow of VHDL Generator for Matlab/ Simulink the conversion of VHDL at by Xilinx＇s System Generator or Altera＇s DSP Builder is introduced. Algorithms to the process should be achieved attention are noted. An integrated configure scheme based on the latest version of the software and hardware is put forward. As an example the complex multiplier is given and simulated using Qurtus Ⅱ.