FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer |
| |
Authors: | Nikolaos KroupisAuthor Vitae Dimitrios SoudrisAuthor Vitae |
| |
Affiliation: | a Department of Electrical & Computer Engineering, Democritus University of Thrace, Greece b School of Electrical & Computer Engineering, National Technical University of Athens, Greece |
| |
Abstract: | In the low power embedded systems design, it is important to analyze and optimize both the hardware and the software components of the system. The power consumption evaluation of the embedded systems is very slow procedure using the instruction-level power models into the simulator. Moreover, a huge number of simulations are needed to explore the power consumption in the instruction memory hierarchy to find the best cache parameters of each hierarchy’s level. In this paper we present a methodology which is aiming to estimate the system power consumption in short time, without simulation. The proposed methodology is based on the fast instruction analysis using instruction level power models, cache memory and memory power models. Based on the proposed methodology a software tool was developed named FILESPPA in order to automate the methodology’s steps for the MIPS processor architectures. The experimental results show the efficiency of the proposed methodology and tool in term of estimation accuracy, reducing the system power estimation time of the simulation technique. |
| |
Keywords: | System modelling Instruction level analysis Architecture exploration Instruction cache Fast exploration |
本文献已被 ScienceDirect 等数据库收录! |