A study of 3D Network-on-Chip design for data parallel H.264 coding |
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| Authors: | Thomas Canhao XuAuthor Vitae Alexander Wei YinAuthor Vitae Pasi LiljebergAuthor Vitae Hannu TenhunenAuthor Vitae |
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| Affiliation: | a Department of Information Technology, University of Turku, Joukahaisenkatu 3-5B, Turku 20520, Finland
b Turku Center for Computer Science, Joukahaisenkatu 3-5B, 6th Floor, Turku 20520, Finland |
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| Abstract: | In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 2D design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications. |
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| Keywords: | Network-on-Chip 3D IC design H 264 Coding Data parallel |
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