高频锁相环的可测性设计

边界扫描是数字电路常用的测试技术，基于IEEE1149．1标准的边界扫描技术对一款CMOS高频锁相环进行了可测性设计，该锁相环最高工作频率达GHz。详细讨论了最高输出频率、输出频率范围和锁定时间参数的测试方案，给出了详细的测试电路和测试方法。对应用该测试方案的锁相环电路增加测试电路前后的电路网表进行了Hspice仿真，仿真结果证明该方法能有效测量锁相环的参数，并且对原锁相环电路的功能影响很小。该测试方法可广泛用于高频锁相环的性能评测和生产测试。

DFT for High -frequency PLL

Boundary scan is usually proposed in design for testability of digital circuits. Based on the standard IEEE1149.1, boundary scan solution of design for testability is applied to a CMOS highfrequency phase locked loop used in VLSI. The highest speed of PLL reaches to GHz. The test method and circuits are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock. In addition,Hspice is Simulated by the increased circuits. different simulation results of PLL with and without test circuits are compared. By the simulation results, the technology of testing is proved effective. So it can be used in function testing and fabrication testing.