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SM2专用指令协处理器设计与实现
引用本文:王腾飞,张海峰,许森.SM2专用指令协处理器设计与实现[J].计算机工程与应用,2022,58(2):102-109.
作者姓名:王腾飞  张海峰  许森
作者单位:1.上海交通大学 电子信息与电气工程学院,上海 200240 2.北京智芯微电子科技有限公司,北京 100192 3.观源(上海)科技有限公司,上海 200241
基金项目:“十三五”国家密码发展基金密码理论课题(SGITZX00YFJS1805255)。
摘    要:国家商用密码算法SM2是基于椭圆曲线密码学(ECC)而制定的公钥密码协议,已被国际标准化组织(ISO)确立为国际标准.在实际应用中,SM2算法计算过程的复杂性使其面临实现效率低的问题,并且在实现过程中还会出现与密钥相关的侧信道信息泄露.为了解决上述问题,设计了一种适用于SM2的专用指令硬件协处理器.协处理器包含接口逻辑...

关 键 词:SM2算法  专用指令  协处理器  流水线技术  现场可编程门阵列(FPGA)

Design and Implementation of SM2 Co-processor with Specific Instructions
WANG Tengfei,ZHANG Haifeng,XU Sen.Design and Implementation of SM2 Co-processor with Specific Instructions[J].Computer Engineering and Applications,2022,58(2):102-109.
Authors:WANG Tengfei  ZHANG Haifeng  XU Sen
Affiliation:1.School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China 2.Beijing Smartchip Microelectronics Technology Company Limited, Beijing 100192, China 3.Viewsource (Shanghai) Technology Company Limited, Shanghai 200241, China
Abstract:The national commercial cryptography algorithmnamed SM2 is a public key cryptographyprotocol based on elliptic curve cryptography(ECC). It has been established as an international standard by the International Organization for Standardization(ISO). In practical applications, the complexity of SM2 algorithm makes it face the problem of low implementation efficiency. And side channel information related to the key may be leaked in the process of implementation. In order to solve these problems, a hardware co-processor with specific instructions for SM2 is designed. The co-processor contains interface logic, fetch unit, decode unit, execution unit, program storage unit, and data storage unit. The implementation process of an instruction can be divided into four stages, which are instruction fetch, decode, execute and write back. The four stages are performed in the way of pipeline, which uses general CPU’s pipeline technology for reference, to improve the performance. After?experimental tests on the platform of Xilinx ZYNQ-7 FPGA, the co-processor can complete the calculation process of SM2 encryption, decryption, signature and verification correctly by automatically executing a sequence of instructions in the program storage unit. The time cost for one scalar multiplication calculation is around 2.25 ms, and 7 146 Slices are occupied. The instruction sequences can be further optimized according to the software implementation mode. It shows that the co-processor has the characteristics of fast speed, small area and high flexibility. Through theoretical analysis, the co-processor can implement a sequence of instructions with constant time, which indicates that it has?certain security against side channel attacks.
Keywords:SM2 algorithm  specific instruction  co-processor  pipelining  field programmable gate array(FPGA)
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