Design and implementation of cascaded H-Bridge multilevel inverter using FPGA with multiple carrier phase disposition modulation scheme |
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| Affiliation: | 1. Department of Electrical and Electronics Engineering, Sakthi Polytechnic College, Sakthi Nagar, Tamil Nadu, India;2. Department of Electronics and Communication Engineering, Velalar College of Engineering and Technology, Erode, Tamil Nadu, India;1. Department of Electrical Engineering, Jadavpur University, Kolkata-700032, West Bengal, India;2. Department of Electrical Engineering, Mizoram University, Aizawl-796004, Mizoram, India;1. Vignan''s Lara Institute of Technology & Science, Guntur, Andhra Pradesh, India;2. Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India;3. Karpagam Academy of Higher Education, Coimbatore, Tamilnadu, India |
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| Abstract: | The paper deals with design of Cascaded H-Bridge Multilevel Inverter (CHB-MLI) with separate DC source to each inverter using multiple carrier Phase Disposition PWM such as symmetric disposition, phase opposition disposition and alternative phase opposition disposition to reduce the Total Harmonic Distortion (THD) and to improve the power quality of the supply voltage and current. In early days, the multilevel inverters are controlled with high frequency PWM method. This is not suitable for high power applications due to the high switching losses. With the help of multiple carrier PWM switching losses in the inverter circuit are reduced, so it can be used for high switchi ng frequency applications. The simulation of proposed system is developed using MATLAB Simulink software. The Performance simulation results are validated through experimental test setup using SPARTAN - 6 FPGA. Simulation results and effectiveness of the proposed method is proved and validated by experimental data. |
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