Design of low power NFSR for RFID system with irregular clock pulse

This Paper describes the Low Power Non linear Feedback Shift Register (NFSR) for Radio Frequency Identification (RFID) System. RFID systems are widely used in many places for product tracking, monitoring the objects and more. The RFID tag stores its distinctive Electronic Product Code (EPC) with related product information within the tag's memory and encrypts this information before its send to the reader. The RFID tags encrypt the data using Pseudo random numbers. Mostly Linear Feedback Shift Register (LFSR) are used to generating pseudo-random sequences which is less security. Nonlinear Feedback Shift Registers (NFSR) is getting to be more famous in recent years because of the insecurity of LFSR. The output sequence of the LFSR is a linear function of the previous stage, it is easily predictable by intruders. Because of this, NFSR is used in many security systems for generating Pseudo-random numbers. The output sequence of NFSR is irrelevant to the previous stage. In this paper, we proposed a new architecture for NFSR, in this model NFSR is controlled by an LFSR with irregular clocking to generate maximal length sequences. The proposed model is designed using 16 nm CMOS technology and operated in the sub-threshold region. The examination is done using Tanner EDA-Industry Standard design environment. The simulation results demonstrate that the irregular clocking architecture reduces the total power consumption by 30 percent.