VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier

Nowadays, Variable digital filters (VDF) play an essential role in the field of communication and signal processing. The desired frequency response of any prototype filter can be obtained by developing an All Pass Transformation (APT) based Variable digital filter (APT-VDF) that maintains an exhaustive control over the cut off frequency. The performance of the APT-VDF is limited by its speed and area utilization. In this paper, the pipelined APT-VDF is modified by developing a new Variable Block Sized Ternary Adder (VBS-TA) and a modified Ternary multiplier for the fast realization of the filter structure. Because, the fundamental arithmetic operations involved in the design of APT-VDF are addition and multiplication. The ternary logic transmits more data through interconnection wire, and hence the ternary logic based arithmetic requires fewer components and interconnections. The proposed VBS-TA increases the speed of the addition process by skipping the carry propagation with the help of ternary compound gates. This VBS-TA can also be used to boost up the speed of the multiplier circuit in the APT-VDF filter. Furthermore, the ternary multiplier is modified by introducing a divide and conquers approach in the partial product generation part. The simulation results show that the proposed APT-VDF overtakes the existing VDFs in terms of delay, power and area utilization. It consumes only 0.289Wpower with a latency of 9.24 ns. Also, it achieves an operating frequency of 210.87 MHz, and it is much better than the existing VDFs.