An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications |
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| Affiliation: | 1. Faculty of Information and Communication Technology, Universiti Tunku Abdul Rahman, Kampar, Perak, Malaysia;2. Department of Electronics, Carleton University, Ottawa, K1S 5B6, Canada;1. Dept. of ECE, Anna University, University College of Engineering Dindigul, Tamilnadu, India;2. Dept. of ECE, Vel Tech. R Dr. S R&D Institute of Science and Technology, Chennai, Tamilnadu, India;3. Dept of EEE, Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India;4. Dept of ECE, Karpagam Academy of Higher Education, Coimbatore, Tamilnadu, India;5. Dept of EEE, Vignan''s Lara Institute of Technology & Science, Guntur, Andhra Pradesh, India;1. Foreign Language School, Ludong University, Yantai, Shandong, 264025, China;2. Department of Basic Courses, Guangdong Police College, Guangzhou, Guangdong, 510230, China;1. Department of Electrical and Electronics Engineering, Mahendra Engineering College, Namakkal, India;2. Department of Electronics and Communication Engineering, Government Polytechnique College, Palacode, Tamil Nadu, India;1. Department of Electronics and Communication Engineering, AAA College of Engineering and Technology, Sivakasi, India;2. Department of Electrical Engineering, Government College of Technology, Coimbatore, India |
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| Abstract: | Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting requirements. This paper introduces a reconfigurable micro-architectural level technique that allows a Reduced Instruction Set Computing (RISC) processor to support IoT applications with different performance and energy trade-off requirements. The processor can be reconfigured into either multi-cycle execution mode (low computational speed with low dynamic power consumption) or pipeline execution mode (high computational speed at the expense of high dynamic power), based on dynamic workload characteristics in IoT applications. Switching between modes is accomplished by exploiting the partial reconfiguration (PR) feature offered by the recent advancements in modern FPGAs. A RISC processor was designed based on the proposed micro-architectural level technique and implemented on FPGA as IoT sensor node. Experimental results demonstrate that the proposed technique with reconfigurable micro-architecture is able to significantly reduce the dynamic energy consumption, compared to conventional multi-cycle and pipeline only micro-architectures, while allowing better performance-energy trade-off in IoT applications. |
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