A 45-Mbit/s CMOS VLSI digital phase aligner

An eight-channel, 45-Mb/s digital phase aligner (DPA) has been fabricated in 2-μm CMOS. The device receives asynchronous serial data at a known average clock frequency and unknown phase, and phase-aligns it with a local clock of the same frequency for subsequent synchronous processing. The all-digital architecture of this device minimizes the need for external components and avoids reliance on analog MOS circuitry. Tracking over a phase excursion range of ±4-bit periods has been demonstrated