用于2.5Gbps千兆以太网发接器的时钟倍频器设计

提出了一种电荷泵锁相环电路实现的适用于 2 .5Gbps千兆以太网发接器要求的高速时钟倍频器的设计方法。为了获得高速时钟 ,设计中采用了双环路的 VCO结构 ,并且运用动态 D触发器来实现高速分频器。同时为了使得 PLL性能更加稳定 ,对电路作了进一步改进 :在 VCO的延迟单元中加了温度补偿部分 ,又采用箝位技术消除电荷泵中电荷重新分配引入的影响。运用 UMC0 .18μm,1.8V CMOS工艺模型 ,在 Cadence的环境下用 spectre S仿真器模拟 ;结果表明设计的时钟倍频电路对于不同的 PV T( P表示工艺变化引起的模型参数的变化 ,VT表示系统工作条件温度和电源电压的变化 )均能得到符合满足 2 .5Gbps千兆以太网发接器要求的时钟倍频信号 ,即使在最坏情况下电路也能保持很好的相位跟踪特性 ,输出静态相位误差平均为 50 ps,整个电路的功耗平均为 35m W。

Design of a High-speed Frequency Multiplier Used in 2.5 Gbps Ethernet Transceiver

A high speed PLL frequency multiplier used in 2.5 Gbps et hernet transceiver is designed.By using dual delay scheme to implement VCO and u sing dynamic D flip flop to implement fr equency divider,high operation frequency is achieved.In addition,a temperature c ompensation technique in VCO is adopted to obtain low temperature sensitivity an d the unity gain amplifier is added in c harge pump to avoid the charge sharing e rror.By using UMC 0.18 μm, 1.8 V CMOS t echnology and spectreS simulator in Cade nce environment,the results show that th is PLL frequency multiplier can meet the requirements of the system under differ ent PVT(Many circuit parameters vary wit h the fabrication process,supply voltage ,and ambient temperature,and we denote t hese effects by PVT),and even in the wor st case the circuit can keep a good phas e jitter performance.The static phase er ror between input and output is 50 ps an d the whole circuit dissipates 35 mW on the average.