The effect of thermal annealing sequence on amorphous InGaZnO thin film transistor with a plasma-treated source–drain structure

In this paper, the effects of thermal annealing and the plasma treatment sequence on the performance of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) without conventional source/drain (S/D) layer deposition were investigated. We fabricated TFTs using two different processes, one where S/Ds were plasma-treated after thermal annealing, the second where the S/Ds were plasma-treated before annealing. The performance of the former exhibited a linear mobility of 4.97 cm²/V s, an on/off ratio of 4.6 × 10⁶, a V_th of 2.56 V, and a subthreshold slope of 0.65 V/decade. However, the TFT parameters of the latter sample were reduced to a linear mobility of 0.07 cm²/V s, an on/off ratio of 1.5 × 10⁵, a V_th of 2.33 V, and a subthreshold slope of 3.54 V/decade. It was shown that the sheet resistance of plasma-treated S/D areas increased after thermal annealing by about three orders of magnitude. As a result, the increase of the sheet resistance caused a decrease of TFT performance.