Analysis of thermal stresses in copper interconnect/low-k dielectric structures

Numerical simulations of thermal stresses in copper (Cu) interconnect and low-k dielectric systems are carried out. The three-dimensional (3-D) finite-element analysis assumes a two-level metal structure connected by a via. Mechanical deformation is generated by thermal expansion mismatches during cooling and cyclic temperature changes. The thin barrier/etch stop layers, as well as oxide or polymer-based low-k dielectric materials, are all taken into account in the model. The stress and deformation fields are examined in detail; salient features having direct implications in device reliability are illustrated with representative contour plots. It is found that the use of low-k material in place of traditional oxide dielectric significantly reduces the triaxial tensile stresses in Cu but enhances plastic deformation, especially in the via region. The compliant low-k material causes the thin barrier layers to bear very high stresses. Deformation in the Cu line and via structure is more affected by the thermal expansion property of the dielectric, but the stresses in the barrier layers are more influenced by the elastic modulus of the dielectric.