A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

The cause of over-erasure in a two-bit nitride storage flash memory cell is investigated. Extra positive charges accumulated above the n/sup +/ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V/sub t/) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state V/sub t/ distribution, which will reduce overerasure significantly.