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65nm三阱CMOS静态随机存储器多位翻转实验研究
引用本文:李丽丽,郭刚,蔡莉,池雅庆,刘建成,史淑廷,惠宁,韩金华.65nm三阱CMOS静态随机存储器多位翻转实验研究[J].原子能科学技术,2017,51(5):909-915.
作者姓名:李丽丽  郭刚  蔡莉  池雅庆  刘建成  史淑廷  惠宁  韩金华
作者单位:1.中国原子能科学研究院 核物理研究所,北京102413;2.国防科学技术大学,湖南 长沙410073
基金项目:国家自然科学基金资助项目(11475272)
摘    要:利用4种不同线性能量转换值的重离子对一款65nm三阱CMOS静态随机存储器(SRAM)进行重离子垂直辐照实验,将多位翻转图形、位置和事件数与器件结构布局结合对器件单粒子翻转截面、单粒子事件截面及多位翻转机理进行深入分析。结果表明,单粒子事件截面大于单个存储单元内敏感结点面积,单粒子翻转截面远大于单个存储单元面积。多位翻转事件数和规模的显著增长导致单粒子翻转截面远大于单粒子事件截面,多位翻转成为SRAM单粒子翻转的主要来源。结合器件垂直阱隔离布局及横向寄生双极晶体管位置,分析得到多位翻转主要由PMOS和NMOS晶体管的双极效应引起,且NMOS晶体管的双极效应是器件发生多位翻转的主要原因。

关 键 词:多位翻转    静态随机存储器    三阱    双极效应    重离子

Experimental Research of Multiple Cell Upsets in 65 nm Triple-well CMOS Static Random Access Memory
LI Li-li,GUO Gang,CAI Li,CHI Ya-qing,LIU Jian-cheng,SHI Shu-ting,HUI Ning,HAN Jin-hua.Experimental Research of Multiple Cell Upsets in 65 nm Triple-well CMOS Static Random Access Memory[J].Atomic Energy Science and Technology,2017,51(5):909-915.
Authors:LI Li-li  GUO Gang  CAI Li  CHI Ya-qing  LIU Jian-cheng  SHI Shu-ting  HUI Ning  HAN Jin-hua
Affiliation:1.China Institute of Atomic Energy, P. O. Box 275-10, Beijing 102413, China;2.National University of Defense Technology, Changsha 410073, China
Abstract:The irradiation tests were performed in a 65 nm triple-well CMOS static random access memory (SRAM) in normal incident angle by using four kinds of heavy ions with different linear energy transfer (LET) values.The single event upset (SEU) cross sections in upsets and in events and the main physical mechanisms of multiple cell upsets (MCUs) were investigated by combining MCUs pattern, position, and counts with the memory cell array layout.The results show that the SEU cross section in events is larger than the area of sensitive nodes in a memory cell while the SEU cross section in upsets is much larger than the area of a cell.The SEU cross section in upsets is larger than SEU cross section in events because of the significant increase in MCUs amount and order, and MCUs become the main source of SEU in SRAM.Moreover, considering of the vertical well isolation layout and the position of parasitic lateral bipolar transistors, most MCUs are induced by parasitic bipolar effect of PMOS and NMOS, of which the parasitic bipolar effect of NMOS is the main cause of MCUs.
Keywords:multiple cell upsets  static random access memory  triple-well  bipolar effect  heavy ion
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