Enhanced pipelined architecture of H.264/AVC intra prediction |
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| Affiliation: | 1. Department of Computer Science and Information Engineering, National Dong Hwa University, 1, Sec. 2, Da-Hsueh Rd., Shou-Feng, Hualien 97401, Taiwan, ROC;2. Department of Computer Science and Information Management, Providence University, 200 Chung Chi Rd., Taichung 43301, Taiwan, ROC;3. Department of Computer Science and Information Engineering, Providence University, 200 Chung Chi Rd., Taichung 43301, Taiwan, ROC;1. Electronic Design Centre, Department of Electronic Engineering, NED University of Engineering and Technology, P.O. Box 75270, Karachi, Pakistan;2. Electrical Engineering Department, United Arab Emirates University, P.O. Box 15551, Al-Ain, UAE;3. IFM Department, Linkoping University, Sweden;1. Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology, Hong Kong;2. Department of Computer and Information Science, University of Macau, Macau;3. School of Computer Science, Harbin Institute of Technology, China;1. National Key Laboratory of Science and Technology on Multi-Spectral Information Processing, Wuhan, China;2. School of Automation, Huazhong University of Science and Technology, Wuhan, China |
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| Abstract: | This paper presents a high-performance encoder for H.264/AVC intra prediction. Due to long data dependency loop of intra 4×4 prediction and complex algorithms, improving encoding speed turns into a stumbling block we have to face. To solve this problem, we first propose a pipelined method in and between macro blocks with new block processing order to accelerate the encoding speed. Benefiting from the pipelined method, reconstructed pixels of up-right blocks are available for two blocks in a macro block which could not take advantage of reconstructed pixels of up-right blocks in JM. So diagonal down left mode and vertical left mode are effective for these two blocks, which ultimately achieves a better bit-rate. Secondly, all 4×4 mode formula sharing method is proposed to reduce the redundancy of predicting formulas. Thirdly, streamlined reconstruction method is applied to improve the performance of reconstruction. CAVLC encoder with three parallel units is proposed to improve entropy coding speed significantly. As a result, it takes 268 cycles to encode a macro block. The experimental results indicate that synthesized into a 0.18 µm CMOS cell library, the new architecture only requires about 238K gates and it is able to encode 1080pHD video sequences at 30 frames per second (fps), at the operating frequency of 56 MHz. |
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| Keywords: | H.264/AVC Intra prediction Pipeline VLSI architecture |
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