基于SiC MOSFET的多芯片并联功率模块不均流研究

针对多芯片功率模块MCPMs(multi-chip power modules)从功率模块布局设计角度对碳化硅SiC(silicon carbide) MOSFET的并联不均流进行了研究。理论分析了造成SiC MOSFET并联不均流的原因,在忽略器件自身差异的情况下,重点分析了非对称布局对功率管并联不均流的影响。在此基础之上,以集成化大功率固态功率控制器SSPC(solid-state power controller)为背景,提出了3种适用于大功率SSPC集成功率模块的非对称布局,分别对3种布局的不均流电流进行了理论分析,并利用Ansoft Q3D提取寄生参数在Saber中对模块的动态开关过程进行仿真。仿真结果表明,通过合理的布局可以减小非对称布局引起的寄生电感不对称对SiC MOSFET并联不均流造成的影响。

Research on Current Imbalance in Paralleling SiC MOSFET Multi-chip Power Modules

In this paper, the current imbalance in silicon carbide(SiC) MOSFET multi-chip power modules(MCPMs) is studied from the aspect of power module layout design. The causes of current imbalance in paralleling SiC MOSFETs are analyzed theoretically; especially, the influence of asymmetric layout on paralleling SiC MOSFETs is analyzed in the case of ignoring differences in devices. On this basis, an integrated high-power solid-state power controller(SSPC) is taken as an example. Three kinds of asymmetric layout for high-power integrated SSPC power module are proposed, and the current imbalance in these layouts is analyzed theoretically. In addition, the dynamic switching process of modules is simulated in Saber using parasitic parameters extracted by Ansoft Q3D. Simulation results show that a proper layout can eliminate the effects of asymmetric parasitic inductance caused by the asymmetric layout on the current imbalance in paralleling SiC MOSFETs.