High Performance GCM Architecture for the Security of High Speed Network |
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Authors: | Vanitha Mohanraj R. Sakthivel Anand Paul Seungmin Rho |
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Affiliation: | 1.Vellore Institute of Technology,Vellore,India;2.The School of Computer Science and Engineering,Kyungpook National University,Daegu,South Korea;3.Department of Media Software,Sungkyul University,Anyang,South Korea |
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Abstract: | Advanced Encryption Standard (AES) is an effective cryptography algorithm for providing the better data communication since it guaranties high security. The Galois/Counter Mode (AES-GCM) has been integrated in various security constrained applications because it provides both authentication and confidentiality. AES algorithm helps to provide data confidentiality while authentication is provided by a universal GHASH function. Since most of existing GCM architectures concentrated on power and area reduction but an compact and efficient hardware architecture should also be considered. In this paper, high-performance architecture for GCM is proposed and its implementation is described. In order to achieve higher operating frequency and throughput, pipelined S-boxes are used in AES algorithm. For a GCM realization of AES, a high-speed, high-throughput, parallel architecture is proposed. Experimental results proves that the performance of the proposed work is around 17% higher than the existing architecture with 3 Gb/s throughput using TSMC 45-nm CMOS technology. |
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