支持存储访问的NoC模拟器的设计与实现

随着片上网络的发展,片上多处理器系统通信性能提高的同时,存储器的访问性能将成为片上多处理器系统的性能瓶颈.目前片上网络的研究主要依赖于模拟器,而现有的片上网络模拟器都不能完成对存储器访问的准确模拟.本文设计并实现了一个能对存储器访问进行模拟的模拟器,为存储器性能的研究提供了一个实验平台;论文通过采用大量访问集对该模拟器进行测试,得出了若干条与存储器访问性能优化相关的片上网络设计建议.

Design and Implementation of a Networks-on-chip Simulator for Memory Access

With the development of NoC,system-on-chip processing power communication performance has been significantly improved,while the memory access performance has become a bottleneck to further improvement of system-on-chip performance.The current research of Networks-on-Chip mainly depends on the simulators,and no existing simulation tool can satisfy the requirements of simulating memory accessing on NoC perfectly.Such a simulator is highly desirable for the research on NoC.In this paper,we design and implement a simulator,which can assume the function of simulating the operations of memory access on NoC,provding a platform for memory performence research.We also use the simulator to evaluate the performance of different accesses sets,obtainting several suggestions about the NoC design for the purpose of optimizing memory access performance.