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Efficient realisation of MOS-NDR threshold logic gates |
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| Authors: | Nunez J. Avedillo M.J. Quintana J.M. |
| Affiliation: | (Instituto de Microelectro′nica de Sevilla (IMSE-CNM-CSIC), Universidad de Sevilla, Spain).; |
| Abstract: | A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure. |
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