叠层CSP封装工艺仿真中的有限元应力分析

叠层CSP封装已日益成为实现高密度、三维封装的重要方法。在叠层CSP封装工艺中,封装体将承受多次热载荷。因此,如果封装材料之间的热错配过大,在芯片封装完成之前,热应力就会引起芯片开裂和分层。详细地研究了一种典型四层芯片叠层CSP封装产品的封装工艺流程对芯片开裂和分层问题的影响。采用有限元的方法分别分析了含有高温过程的主要封装工艺中产生的热应力对芯片开裂和分层问题的影响,这些封装工艺主要包括第一层芯片粘和剂固化、第二、三、四层芯片粘和剂固化和后成模固化。在模拟计算中发现:(1)比较三步工艺固化工艺对叠层CSP封装可靠性的影响,第二步固化工艺是最可能发生失效危险的;(2)经过第一、二步固化工艺,封装体中发现了明显的应力分布特点,而在第三步固化工艺中则不明显。

Finite Element Stress Analysis by Packaging Process Simulation in a Stacked Chip Scale Package

Stacked chip scale packaging (SCSP) has been an increasingly important approach for realizing high density 3-D packaging. During SCSP process, package will endure several thermal loadings, such as die attach (DA) cure, post-molding cure and reflow. Thermal stress may result in die crack or delamination before package is finished if thermal mismatch between internal packaging materials is too much. In this study, packaging process for a typical four-chip SCSP product, FTA073, is studied in detail. Finite element analysis (FEA) has been applied in three major process steps which experience temperature change for package failu res in die crack or delamination, including the 1st DA cure (cure I), the 2nd 3rd 4th DA cure (cure II) and post-molding cure (cure III). Our process simu lation demonstrates that cure II would be the most destructive by comparing the influence of these three curing processes on SCSP reliability. It is also found that, in cure I and cure II a certain distribution stress with typical character istics is formed on package block which consists of 15 unit packages, however, n o such characteristics was formed in step cure III. Our investigation would be b eneficial to reducing package failures and increasing yields during packaging pr ocess.