| 基于集成频率合成器的锁相环设计 |
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| 引用本文： | 郝绍杰. 基于集成频率合成器的锁相环设计[J]. 国外电子测量技术, 2008, 27(1): 12-15 |
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| 作者姓名： | 郝绍杰 |
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| 作者单位： | 中国电子科技集团公司第41研究所,青岛,266555 |
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| 摘 要： | 本文介绍了采用直接数字频率合成器(DDS)和集成锁相频率合成器PE3236设计2.4G-4.4G Hz本振信号源的新方法,与传统采用小数分频的设计方法相比,具有电路简单、功耗低、体积小等优点,经制作实验电路板验证,试验电路的单边带相位噪声和频率分辨率都达到了预先的设计要求,试验取得了预期的效果.
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| 关 键 词： | 直接数字频率合成器 集成频率合成器 单边带相位噪声 |
PLL design based on integrate frequency synthesizer |
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| Hao Shaojie. PLL design based on integrate frequency synthesizer[J]. Foreign Electronic Measurement Technology, 2008, 27(1): 12-15 |
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| Authors: | Hao Shaojie |
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| Abstract: | This paper presents a new method of designing a local signal source which frequency ranges from 2.4 GHz to 4.4 GHz. The new method adopts the direct digital synthesizer (DDS) and integrate frequency synthesizer PE3236. Comparing with the traditional designing method which using the fractional-N architecture, the advantages of this new method includes simple circuit, low dissipation, small size. The circuit boards produced experimental verification, testing circuits and frequency single-sideband (SSB) phase noise have reached a resolution in advance of the design requirements, and test achieved the desired results. |
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| Keywords: | direct digital synthesizer (DDS) integrate frequency synthesizer SSB phase noise |
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