A novel low-power,low-offset,and high-speed CMOS dynamic latched comparator |
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Authors: | HeungJun Jeon Yong-Bin Kim |
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Affiliation: | (1) Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA |
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Abstract: | A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock
signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch
stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the
latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power
supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage
difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.
In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator
is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after
calibration. |
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Keywords: | |
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