一种SOC微处理器IP核的优化设计

该文提出了多种改善微处理器设计的优化方法.在系统结构上,采用四级流水结构,改善了微处理器的执行效率;为了解决数据相关问题,采用了bypass技术,并进一步提高了流水线的效率.在CPU结构上,采用纯组合逻辑电路和改进的ALU算法,来提高处理器的速度.最后,对该CPU核完成了仿真和综合,并在FPGA上成功地实现.实验结果表明设计的SOC处理器在指令上与通用的PIC16C57的处理器兼容,而执行效率为其4倍,系统时钟可达到40MHz以上.

Optimization & Design of A SOC CPU IP Core

several improved design methods have been introduced.In system architecture,two-pipeline architecture in PIC16C57 is replaced by a four-pipeline architecture,and this method is employed to improve MCU's execution efficiency.The bypass technique is employed to resolve the data correlation.In CPU architeture,the ALU with purely combinational circuit and improved algorithms are employed to get high speed.Last,the CPU has been successfully simulated and synthesized,and has been implemented in FPGA.Experiment results show the instruction set of our CPU is compatible with that of PIC16C57,its execution efficiency is 4 times as high as that of PIC16C57,and its system clock reaches above 62.9MHz.