分离栅式快闪存储器擦除性能的工艺优化

随着电子产品的普及,分离栅式快闪存储器作为闪存的一种,由于具有高效的编程速度以及能够完全避免过擦除的能力,无论是在单体还是在嵌入式产品方面都得到了人们更多的关注。随着闪存市场高集成度的发展需求,分离栅式快闪存储器的尺寸也在逐渐地缩小。从结构和工艺优化方面探讨在这一微缩过程中,如何有效提高分离栅式快闪存储器的擦除效率。通过实验发现通过形成非对称性浮栅结构,优化浮栅到擦除栅侧的结构形貌,可以显著改进分离栅式工艺快闪存储器的擦除性能。

Process Optimization to Improve Erase Performance in Split-gate Flash

As of the popularity of various electronic products, the split-gate flash, one kind of the flash memories, due to its highly efficient programming speed and the ability to completely avoid over-erase issue, got more and more attention both in stand-alone and embedded applications. With the high density requirement in flash memory market, the cell size of the split-gate flash has to be continuous shrinking. The paper studied on how to improve erase performance in the shrinked split-gate flash, through cell structure and process optimization. With the optimized floating gate profile at erase gate side, the erase efficient of such kind of split-gate flash can be greatly improved.