1.5-6GHz增益和噪声系数稳定的两级超宽带CMOS低噪声放大器设计与性能模拟

 针对UWB应用设计实现了一个1.5-6GHz的两级CMOS低噪声放大器(LNA). 通过引入共栅(CG)和共源(CS)结构以获得宽范围内的输入匹配，采用电流镜和峰化电感进行电流复用，所提出的LNA实现了非常平坦化的功率增益和噪声系数(NF). 经标准0.18μm CMOS工艺实现后，版图后模拟结果表明在1.5-5GHz频率范围内功率增益(S21)为11.45±0.05dB，在2-6GHz频率范围内噪声系数(NF)为5.15±0.05dB，输入损耗(S11)小于-18dB. 在5GHz时，模拟得到的三阶交调点(IIP3)为-7dBm，1dB压缩点为-5dBm.在1.8V电源电压下，LNA消耗6mA的电流，版图实现面积仅为0.62mm^2.

Design and Performance Simulation of a 1.5-6 GHz Two-Stage UWB CMOS LNA with Extra Flat Gain and NF

A two-stage 1.5-6GHz CMOS Low Noise Amplifier(LNA) for Ultra-Wide-Band(UWB) applications is presented. By introducing common-gate(CG) and common-source(CS) stages to obtain broad-band input matching and current mirror to reuse current through a peaking inductor, the proposed LNA has achieved extra flat power gain and Noise Figure(NF). This LNA has been implemented by a 0.18μm standard CMOS process. Post simulation results have indicated that the power gain(S21) achieves 11.45±0.05dB over the wide frequency band of 1.5-5GHz, and NF maintains 5.15±0.05dB from 2GHz to 6GHz with input return loss(S11)<-18dB in the entire band. The simulated input-referred third-order intercept point(IIP3) at 5GHz is -7dBm, while the 1dB compression point is -5dBm. It draws 6mA from 1.8V supply and occupies an area of only 0.62mm^2.