| 循环移位可编程序逻辑阵列的可测试性设计 |
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| 引用本文： | 韩继国. 循环移位可编程序逻辑阵列的可测试性设计[J]. 微电子学与计算机, 1993, 10(9): 21-23 |
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| 作者姓名： | 韩继国 |
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| 作者单位： | 骊山微电子公司 陕西临潼 |
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| 摘 要： | 本文研究了一种“芯片内部自测式”可编程序逻辑阵列(Built-in Sclf Tcst PLA)的设计方法:循环移位PLA(简称CS-PLA)法.CS-PLA与其他PLA可测试性设计方法相比,具有故障覆盖率高、对电路速度影响小、测试生成简单等特点,当PLA嵌入在芯片内部时,不需要单独的测试状态。其芯片面积成本随PLA的规模增大而降低,因此CS-PLA特别适用于大规模“嵌入式”PLA.
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| 关 键 词： | 逻辑阵列 可测试性 设计 循环移位 |
A Testable Design of Circular-shift PLAs |
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| Han Jiguo. A Testable Design of Circular-shift PLAs[J]. Microelectronics & Computer, 1993, 10(9): 21-23 |
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| Authors: | Han Jiguo |
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| Abstract: | In this paper we investigate a design method of a built-in self-test PLA: circular-shift PLA(CS- PLA). It offers many advantages compared to existing methods: hardware is low, testing is at normal operating speed, test generation is simple, a very wide class of faults are covered and only one self-test mode is required. It is suitable for large embedded PLAs. |
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| Keywords: | Testable design Circular-shift PLA PLA |
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