Local clustering 3-D stacked CMOS technology for interconnect loading reduction |
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Authors: | Xinnan Lin Shengdong Zhang Xusheng Wu Chan M |
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Affiliation: | Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China; |
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Abstract: | A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower. |
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