A Method of Formal Verification of Cryptographic Circuits |
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| Authors: | Kanji Hirabayashi |
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| Affiliation: | (1) Toshiba Research and Development Center, TTC, Komukai Toshiba-cho, Kawasaki, 210-0901, Japan |
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| Abstract: | In this letter we report the formal verification of encryption and decryption circuits. After we describe algebraically a simple modular arithmetic circuit at both function and logic levels, we apply the symbolic manipulation of Mathematica. |
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| Keywords: | formal verification encryption decryption |
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