Simulation of dynamic input buffer space in multistage interconnection networks

This paper presents a simulation study of a new dynamic allocation of input buffer space in multistage interconnection networks (MINs). MINs are composed of an interconnected set of switching elements (SEs), connected in a specific topology. The SEs are composed of input and output buffers which are used to store received and forwarded packets, respectively. The performance of these networks depends on the design of these internal buffers and the clock mechanism in synchronous MINs. Various cycle models exist which include the big cycle, small cycle and the smart cycle, each of which provides a more efficient cycle timing. The smart cycle model achieves a superior performance by using output buffers and acknowledgement. However, it suffers from lost and out-of-order packets at high traffic loads. This paper, presents a variation of the smart cycle model, whereby, the input buffer space of each SE is allocated dynamically as a function of traffic load, in order to overcome the above-mentioned drawbacks. A shared buffer pool is provided, which supplies the required input buffer space as required by each SE. Simulation results are presented, which show the required buffer pool for various network sizes and for different network loads. Also, comparison with a static allocation scheme shows an increased network throughput, and the elimination of lost and out-of-order packets at high traffic loads.