A deep learning based latency aware predictive routing model for network-on-chip architectures

Network on Chip (NoC) is an evolving platform for communications related applications, which are executed on a single silicon chip. There are several routing models in NoC architectures, but the accuracy of these models is limited, and the existing models are degraded because of over and under fitting issues. This research introduces the new deep learning-based latency aware predictive routing model for on-chip networks to route packets with better performance and power efficiency. The deep learning model used in this research is a new convolutional residual gated recurrent unit (CRGRU) with queuing theory. Moreover, the source and channel queuing delay is comprised of features to learn spatial and sequential information that improves the overall prediction accuracy. This router is modified by the intrusion of the Router States Monitor unit and the CRGRU hardware engine. The work is executed using the Xilinx platform, and the performance measures like latency and throughput are obtained by varying the network size as $4\times 4$, $8\times 8$, and $12\times 12$ and also varying the buffer space and length as $L=4,B=9$, $L=9,B=4$, and $L=14,B=3$, respectively. In addition, the squared correlation coefficient (SCC) and normalized root mean square error (NRMSE) are evaluated and compared with existing learning models to validate the proposed model.