Experimental study of hot-carrier effects in LDMOS transistors

Hot-carrier currents and the induced degradation mechanisms in lateral double-diffused MOS (LDMOS) transistors for smart power applications are investigated in detail. Three different regions within the device where significant hot-carrier generation can occur depending on bias as well as device technological parameters have been identified. Guidelines to suppress the degradation mechanisms involving the two lightly doped regions of the device not overlapped by the gate electrode, responsible for the stronger device degradation, are provided. Devices optimized according to the given guidelines have been fabricated and demonstrate a strong hot carrier resistance