可复用SVPWM IP核的设计与实现

为了提高全数字交流伺服系统中各个功能模块的可复用性，缩短开发周期，分析了可复用IP核的设计方法与准则，依据电压空间矢量脉宽调制原理，采用自顶向下的设计方法，给出了系数整定、扇区判断、时间计算与分配、数据锁存以及PWM生成等模块的设计方法，实现了一种采用FPGA和可复用知识产权核（IPCore）相结合的全数字化速度伺服系统。仿真结果表明，该系统能够在8μs内完成矢量控制算法，其电流环、速度环的采样频率可达到20kHz以上，具有响应快速，调速范围帘等优点．此IP核功能正确．可以作为一个独立的模块嵌入到今教宰交流伺服系统中。

The design and implementation of the reused SVPWM IP core

To enhance the reusability and reduce the development cycle,the scheme implemented with Field Programable Gate Array(FPGA)and reused IP core is proposed.The design method and criterion are analyzed,and take the design of space vector PWM module as the example.Based on the principle of SVPWM,the functional modules such as scaler,sector finder,time calculation,time assignment,data latch and PWM generator,which are implemented adopting top-to-down design method,the simulation and verification based-on FPGA are given.The simulation results verify the functionality of modules,and it can be used in the design of digital AC servo system.