基于FPGA的高速Link接口收发器设计

在数字信号处理领域,采用DSP＋FPGA的联合方案是最流行的选择,而DSP与FPGA之间数据通信的速度则直接影响着信号处理的效率。因此,高速率、大数据带宽的数据实时通讯就成为了现代信号处理系统的关键。本文提出并实现了一种基于ADI TigerSHARC101 Link协议的高速通信收发器,能同时在时钟的上升沿和下降沿收发数据,实现FPGA与DSP、以及FPGA片间的无缝连接,经ISE布线验证,整个系统仅占用FPGA少量逻辑资源,最高工作频率超过270MHz,数据传输率可达4.32Gbps,使片间数据通信不再成为信号处理的瓶颈。具有很强的工程应用价值。

High-speed Link Port Transmitter / Receiver Based on FPGA

For classic digital signal processing design, DSP ＋ FPGA scheme was the most popular, However, the efficiency of processing system was greatly restricted by data transmitting rate between DSP and FPGA. Therefore, high-rate, wide data bandwidth data real-time transceiver become the vital part of modem signal processing system. In this paper, a high-rate transceiver based on ADI TigerSHARC101 Link protocol was presented, which can completing data exchange both on rising edge and falling edge of elk. And the seamless connection between FPGA and DSP was achieved. After ISE synthesis and routing, the highest work clock of whole system can achieve 270MHz, with only few FPGA resources used. The equivalent transmitting rate was 4.32Gbps, so that data exchange won＇t be the bottleneck of whole system, indicating very high engineering values.