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A design of time-optimum and register-number-minimum systolic convolvers
Authors:Hiroshi Umeo
Affiliation:

Osaka Electro-Communication University Neyagawa-shi, Hatsu-cho, 18-8, Osaka, 572, Japan

Abstract:We present an optimum bit-parallel/word-sequential systolic convolver. Our design is the best one among the previous many convolvers in the sense that its optimality in time and space performances is simultaneously attained without augmenting any global control, broadcasting, initial-data-preloading, and/or multi-sequential or parallel I/O ports which were allowed in most of the previous designs. As an application of our convolver we give a systolic polynomial divider which can compute the polynomial division in exactly n + O(1) optimum steps on min(nm, m)/2]+O(1) systolic cells for the division of any degree n polynomial by any degree m polynomial (n greater-or-equal, slanted m).
Keywords:VLSI design  systolic convolver  time optimum  register number minimum  real-time pattern matcher  time-optimum polynomial divider  systolic array  systolic algorithm
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