A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator |
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Authors: | Yang Siyu Zhang Hui Fu Wenhui Yi Ting Hong Zhiliang |
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Affiliation: | State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China |
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Abstract: | A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72 μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step. |
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Keywords: | successive approximation register A/D differential time domain comparator |
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