1.2V低功耗时钟发生器设计

基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现。电路使用1.2 V单一电源电压,并在片上集成了环路滤波器。其中,振荡器为电流控制、全差分结构的五级环形振荡器。该信号发生器可以产生的时钟频率范围为12.5～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk=75 ps,rms=8.6 ps;Cycle-to-Cycle抖动为:pk-pk=132 ps,rms=14.1 ps。电路的面积为84μm2。

Design of A 1.2V Low-Power Clock Generator

This phase-locked-loop clock generator is based on SMIC 65 nm CMOS process,which focuses on low power and low jitter design.The generator is droved by 1.2 V single power supply and the loop filter is integrated on the chip.A full differential ring-oscillator consisted of five delay cells is used to generate 100-800 MHz clock,and output frequency range is 12.5 -800 MHz.The power consumption is 1.54 mW at 800 MHz.The period jitter (pk-pk) is 75 ps and period jitter (rms) is 8.6 ps; the cycle-to-cycle jitter (pk-pk) is 132 ps and cycle-to-cycle (rms) is 14.1 ps.The area of the circuit is 84 μm2.