| NCL电路并行处理结构研究 |
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| 引用本文： | 崔亚磊,戴紫彬. NCL电路并行处理结构研究[J]. 计算机工程与应用, 2010, 46(1): 54-56. DOI: 10.3778/j.issn.1002-8331.2010.01.018 |
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| 作者姓名： | 崔亚磊 戴紫彬 |
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| 作者单位： | 解放军信息工程大学 电子技术学院，郑州 450004 |
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| 摘 要： | 针对NCL电路数据编码方式的特点，提出了一种并行数据处理的NCL电路结构，通过同时对两路双轨编码数据流的并行处理，提前计算出下一个无效数据，缩短了无效数据维持时间。此结构应用到4×4乘法器的设计，采用COMS 0.18 ?滋m工艺，乘法器在非流水模式下和2级流水模式下分别进行了综合、布局布线和仿真，与传统NCL 4×4乘法器相比，无效数据维持时间分别缩短了32.9%和33.2%。
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| 关 键 词： | 零约束逻辑电路 并行处理 异步电路 |
| 收稿时间： | 2008-09-25 |
| 修稿时间： | 2008-12-25 |
Research of NCL circuits parallel processing architecture |
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| CUI Ya-lei,DAI Zi-bin. Research of NCL circuits parallel processing architecture[J]. Computer Engineering and Applications, 2010, 46(1): 54-56. DOI: 10.3778/j.issn.1002-8331.2010.01.018 |
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| Authors: | CUI Ya-lei DAI Zi-bin |
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| Affiliation: | Institute of Electronic Technology，the PLA Information Engineering University，Zhengzhou 450004，China |
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| Abstract: | This paper proposes a framework of NCL circuits paraHel processing for reducing the NCL data wave time.Mter the two dual-rail data waves through the parallel circuits,the next null data has been calculated,SO,the data to data cycle time has been shortened.Taking the 4x4 multiplier for example,the circuits have been fabricated in 0.18 Izm CMOS process.In the case of non-pipelining module,T_(DD) has reduced 32.9%and in the case of 2 stage pipelining module,T_(DD) has reduced 33.2%. |
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| Keywords: | Null Convention logic(NCL)circuits parallel processing asynchronous circuits |
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