| 数字电路多加权集随机测试生成方法 |
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| 引用本文： | 谢永乐,陈光(礻禹). 数字电路多加权集随机测试生成方法[J]. 计算机辅助设计与图形学学报, 2002, 14(6): 571-573 |
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| 作者姓名： | 谢永乐 陈光(礻禹) |
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| 作者单位： | 1. 电子科技大学自动化系,成都,610054;四川大学制造科学与工程学院,成都,610065
2. 电子科技大学自动化系,成都,610054 |
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| 摘 要： | 提出一种基于确定性完备测试集的数字集成电路多加权集随机测试生成方法 .通过引入搜索与迭代算法 ,将完备测试集分成若干测试子集 ,每一子集对应一个权集 ,即产生该子集中测试矢量的被测电路各主输入端取‘1’值的概率组合 .该方法与文献 [2 - 3]的结果相比 ,在测试序列长度或硬件开销上获得了改善 ,对大规模集成电路的内建自测试尤为适用
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| 关 键 词： | 故障诊断 测试生成器 加权随机测试 多加权集 超大规模集成电路 |
Random Test Generation of Digital Circuit with Multiple Weighted Set |
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| Xie Yongle ,) Chen Guangju ) ). Random Test Generation of Digital Circuit with Multiple Weighted Set[J]. Journal of Computer-Aided Design & Computer Graphics, 2002, 14(6): 571-573 |
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| Authors: | Xie Yongle ) Chen Guangju ) ) |
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| Affiliation: | Xie Yongle 1,2) Chen Guangju 1) 1) |
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| Abstract: | A new methodology based on a deterministically complete test set is proposed. The method described arises from the division of complete test set into several test subsets and each subset corresponds to a weight set. A certain weight set comprises of the probabilities of producing a logic "1" to each primary input of circuits under test. The method provides effective improvement in the test length of test hardware overhead compared with the previously published results , it is suitable for BIST of VLSI especially. |
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| Keywords: | fault diagnosis test pattern generator weighted random test multiple weight set VLSI |
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