| 一种提高遥测信号处理器测试性方法 |
| |
| 引用本文： | 朱党杰,蒋学东. 一种提高遥测信号处理器测试性方法[J]. 电子科技, 2013, 26(6): 31-33,36 |
| |
| 作者姓名： | 朱党杰 蒋学东 |
| |
| 作者单位： | (中国空空导弹研究院 通信技术研究所,河南 洛阳 471009) |
| |
| 摘 要： | 针对遥测信号处理器的设计原理,增加少量硬件电路,利用其自身FPGA剩余逻辑资源完成自检模块设计,实现了信号处理器BIT测试功能,提高了信号处理器在挂机状态下的测试覆盖率和故障检测率。
|
| 关 键 词： | FPGA BIT 测试性 |
A Method for Enhancing the Testability of Telemetry Signal Processor |
| |
| ZHU Dangjie , JIANG Xuedong. A Method for Enhancing the Testability of Telemetry Signal Processor[J]. Electronic Science and Technology, 2013, 26(6): 31-33,36 |
| |
| Authors: | ZHU Dangjie JIANG Xuedong |
| |
| Affiliation: | (Communication Technology Research Institute,China Airborne Missile Academy,Luoyang 471009,China) |
| |
| Abstract: | The design principle of telemetry signal processor is introduced.A method by introducing an additional hardware circuit and taking advantage of the rest logic resource in FPGA is given to enhance the fault detection rate and test coverage of telemetry signal processor hanging on the aerobat.BIT of telemetry signal processor is realized by designing self-checking module based on this method. |
| |
| Keywords: | FPGA BIT testability, |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
| 点击此处可从《电子科技》浏览原始摘要信息 |
|
点击此处可从《电子科技》下载全文 |
|
