| 基于排队论的UM-BUS总线性能建模与评估 |
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| 引用本文： | 张少楠,邱柯妮,张伟功,王晶,郑佳欣,白瑞英,朱晓燕. 基于排队论的UM-BUS总线性能建模与评估[J]. 计算机科学, 2017, 44(Z6): 504-509 |
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| 作者姓名： | 张少楠 邱柯妮 张伟功 王晶 郑佳欣 白瑞英 朱晓燕 |
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| 作者单位： | 首都师范大学信息工程学院 北京100048;首都师范大学高可靠嵌入式系统技术北京市工程研究中心 北京100048,北京成像技术高精尖创新中心 北京100048;首都师范大学电子系统可靠性技术北京市重点实验室 北京100048,北京成像技术高精尖创新中心 北京100048;首都师范大学高可靠嵌入式系统技术北京市工程研究中心 北京100048,北京成像技术高精尖创新中心 北京100048;首都师范大学电子系统可靠性技术北京市重点实验室 北京100048,首都师范大学信息工程学院 北京100048,首都师范大学信息工程学院 北京100048;首都师范大学电子系统可靠性技术北京市重点实验室 北京100048,首都师范大学信息工程学院 北京100048;首都师范大学高可靠嵌入式系统技术北京市工程研究中心 北京100048 |
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| 基金项目： | 本文受北京市属高等学校创新团队建设与教师职业发展计划项目(IDHT20150507),北京市教育委员会科技计划一般项目(SQKM201710028016)资助 |
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| 摘 要： | UM-BUS总线是一种具有动态容错能力和远程穿透式访问能力的高速串行总线,其性能模型对UM-BUS的综合评估和优化设计具有重要意义。针对UM-BUS总线系统,提出基于排队论的性能评估的模型,该模型定性描述了总线上不同节点之间的数据流关系、数据包到达节点的特征以及在节点处等待处理的特性；定量分析了不同数据包在总线信道传输的最大延迟、最小延迟以及平均延迟。在MATLAB平台上测试了数据包在总线上的等待时间和传输时间。实验结果可以帮助设计者快速分析总线在实际应用系统中的特性并对其进行优化配置,提高总线的使用效率。
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| 关 键 词： | UM-BUS总线 排队论 性能建模 传输延迟 |
Queuing Theory-guided Performance Evaluation on Reconfigurable High-speed Device Connected Bus |
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| ZHANG Shao-nan,QIU Ke-ni,ZHANG Wei-gong,WANG Jing,ZHENG Jia-xin,BAI Rui-ying and ZHU Xiao-yan. Queuing Theory-guided Performance Evaluation on Reconfigurable High-speed Device Connected Bus[J]. Computer Science, 2017, 44(Z6): 504-509 |
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| Authors: | ZHANG Shao-nan QIU Ke-ni ZHANG Wei-gong WANG Jing ZHENG Jia-xin BAI Rui-ying ZHU Xiao-yan |
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| Affiliation: | College of Information Engineering,Capital Normal University,Beijing 100048,China;Beijing Engineering Research Center of High Reliable Embedded System,Capital Normal University,Beijing 100048,China,Beijing Advanced Innovation Center for Imaging Technology,Beijing 100048,China;Beijing Key Laboratory of Electronic System Reliability and Prognostics,Capital Normal University,Beijing 100048,China,Beijing Advanced Innovation Center for Imaging Technology,Beijing 100048,China;Beijing Engineering Research Center of High Reliable Embedded System,Capital Normal University,Beijing 100048,China,Beijing Advanced Innovation Center for Imaging Technology,Beijing 100048,China;Beijing Key Laboratory of Electronic System Reliability and Prognostics,Capital Normal University,Beijing 100048,China,College of Information Engineering,Capital Normal University,Beijing 100048,China,College of Information Engineering,Capital Normal University,Beijing 100048,China;Beijing Key Laboratory of Electronic System Reliability and Prognostics,Capital Normal University,Beijing 100048,China and College of Information Engineering,Capital Normal University,Beijing 100048,China;Beijing Engineering Research Center of High Reliable Embedded System,Capital Normal University,Beijing 100048,China |
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| Abstract: | UM-BUS is a high-speed serial BUS which has the ability of dynamic fault-tolerance and remote access.It is essential to implement performance modeling in advance when making comprehensive evaluation and optimization design of the bus.Targeting this issue,a performance evaluation model was proposed based on queuing theory in this paper.On one hand,this model describes the dataflow relationship among different slave nodes and the characteristics of packets waiting and arriving time to slave nodes qualitatively.On the other hand,this model analyzes the maximum,minimum and average delay of the different packets in the lane transmission quantitatively.Testing on the MATLAB platform provides packet waiting time and transmission time on the bus.Experimental results can help designers to well understand the bus system features in practical applications,so they can carry out reconfigurations and improve the efficiency of UM-BUS. |
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| Keywords: | UM-BUS Queuing theory Performance evaluation Transmission delay |
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