A 50-ns 256 K CMOS split-gate EPROM

A high-speed 32 K×8 CMOS EPROM has been designed and implemented in a polycide 1.2-μm n-well epi CMOS technology. A high-read-current split-gate EPROM cell combined with address transition detection-based SRAM-like precharge, equalization, and clocked differential sensing schemes has resulted in a typical address access time of less than 50 ns. The typical power dissipation at 18.2 MHz is 60 mW. Row redundancy is used to enhance the yield and the part has been designed to be compatible with plastic packaging