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多天线系统中小数倍时延补偿及其FPGA实现
引用本文:李小娅,刘源源,张蓉,雷维嘉,谢显中.多天线系统中小数倍时延补偿及其FPGA实现[J].数字通信,2014(2):45-49.
作者姓名:李小娅  刘源源  张蓉  雷维嘉  谢显中
作者单位:重庆邮电大学 移动通信重庆市重点实验室,重庆400065;重庆邮电大学 移动通信重庆市重点实验室,重庆400065;重庆邮电大学 移动通信重庆市重点实验室,重庆400065;重庆邮电大学 移动通信重庆市重点实验室,重庆400065;重庆邮电大学 移动通信重庆市重点实验室,重庆400065
基金项目:重庆市自然科学基金(CTSC2011jjA40006);重庆市教委科学技术研究项目( KJ120501, KJ120502)。
摘    要:研究多天线系统中2路来自同一信号源、不同时延的信号进行延时补偿的方案和FPGA实现方法.时延补偿由小数倍和整数倍的时延补偿两部分组成,主要采用对超前的数据进行延迟来实现,其中,小数倍时延采用sinc函数延迟滤波器实现,整数倍时延采用D触发器实现.在消除这些延时之后,再控制数据选择器,选择合适的数据输出,实现2路数据的延迟补偿.设计通过MATLAB与FPGA的联合仿真进行了验证.

关 键 词:时延补偿  小数倍延  sinc函数滤波器  FPGA
收稿时间:1/8/2014 12:00:00 AM

Fractional delay compensation and it's FPGA implementation in multi antenna system
LI Xiaoy,LIU Yuanyuan,ZHANG Rong,LEI Weijia and XIE Xianzhong.Fractional delay compensation and it's FPGA implementation in multi antenna system[J].Digital Communication,2014(2):45-49.
Authors:LI Xiaoy  LIU Yuanyuan  ZHANG Rong  LEI Weijia and XIE Xianzhong
Affiliation:Chongqing Key Lab of Mobile Communications Technology & Institute of Personal Communications,Chongqing University of Posts and Telecommunications,Chongqing 400065, P.R.China;Chongqing Key Lab of Mobile Communications Technology & Institute of Personal Communications,Chongqing University of Posts and Telecommunications,Chongqing 400065, P.R.China;Chongqing Key Lab of Mobile Communications Technology & Institute of Personal Communications,Chongqing University of Posts and Telecommunications,Chongqing 400065, P.R.China;Chongqing Key Lab of Mobile Communications Technology & Institute of Personal Communications,Chongqing University of Posts and Telecommunications,Chongqing 400065, P.R.China;Chongqing Key Lab of Mobile Communications Technology & Institute of Personal Communications,Chongqing University of Posts and Telecommunications,Chongqing 400065, P.R.China
Abstract:This paper studies the delay compensation scheme and it's FPGA compensation of 2 signals that come from the same source and have different time delay in multi antenna systems. The delay compensation is composed of fractional and integer delay compensation, which is mainly realized by delaying the advanced data. Fractional delay compensation is real- ized by sinc filter; integer delay compensation is realized by D flip flop. Then we export appropriate data by controlling the multiplexer to realize the delay compensation of 2 signals after eliminating these delays. The design is validated by cosimu- lation of MATLAB and FPGA.
Keywords:delay compensation  fractional delay  sinc filter  FPGA
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