A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed-pattern noise reduction

A novel logarithmic response CMOS image sensor fabricated by 0.25-/spl mu/m CMOS logic process is proposed. The new cell has an output voltage swing of 1 V in the targeted illumination range, which makes it less susceptible to noises in the readout system. Furthermore, the proposed new cell with in-pixel CDS control drastically reduces the fixed pattern noise in logarithmic mode CMOS APS. Comparing with a conventional pixel, a reduction of 10 times in fixed-pattern noise is demonstrated in the new logarithmic response CMOS image sensor.